The present invention relates to a MOS field-effect transistor (MOSFET), and more particularly to a MOSFET with a low on resistance Ron which may be fabricated using simple fabrication techniques such as trench processing.
As is known, a search has been underway for some time now for ways to reduce the on resistance Ron of MOSFETs, especially that of power MOSFETs. U.S. Pat. No. 5,216,275, for example, describes a power semiconductor device which is basically constructed in the manner described in the introduction thereof the drift path of this semiconductor device is provided with a so-called xe2x80x9cvoltage sustaining layerxe2x80x9d, which comprises vertical p- and n-type semiconducting regions which lie next to one another and alternate with one another and between which an insulating layer made of silicon dioxide is provided. FIG. 4 shows a MOSFET which is exemplary of a prior art semiconductor device of this type. Similar Device with oxdye between n and p layers is described in U.S. Pat. No. 4,754,310/Coe.
This known MOSFET comprises a semiconductor body 1 having an n+-doped drain contact zone 2; mutually alternating n-type and p-type semiconductor zones 3 and 4, respectively, 7 which are isolated from one another by an insulating layer 5 made of for example, silicon dioxide and p-type semiconductor zones (xe2x80x9cbodyxe2x80x9d zones) 6 and n-type semiconductor zones 7 embedded in the zones 6.
Silicon is usually used for the semiconductor body 1, although other materials may also optionally be used. The conductivity types specified may also optionally be reversed.
Gate electrodes 9 made of doped polycrystalline silicon are embedded in an insulating layer 8 made, for example, of silicon dioxide or silicon nitride and are provided with a terminal G. A metal layer 10 made of aluminum, for example, makes contact with the n-type zones 7 and is is provided with a source terminal S, which may be grounded. A drain voltage +UD is applied to the n+-doped semiconductor layer 2, which is provided with a drain terminal D.
With the applied voltage +UD, the zones 3 and 4 are mutually depleted of charge carriers. If, in the zones 3 and 4, which run in the form of pillars between the two main surfaces A and B, respectively, of the semiconductor body 1, the total quantity of the n-type doping and of the p-type doping is about the same or so low that the zones 3 and 4 are completely depleted of charge carriers before a breakdown occurs, then such a MOSFET can block high voltages and nevertheless have a low on resistance Ron. On account of the insulating layer 5 between the n-type zones 3 and the p-type zones 4, the p-type zones 4 arranged underneath the zones 6 in this case serve as grounded field plates for the n-type zones 3 as long as the latter are not completely depleted of charge carriers.
It is an object of the present invention, therefore, to provide a MOSFET which has a low Ron comparable to prior art MOSFETs but is considerably simpler to produce.
A MOSFET according to the present invention comprises:
a semiconductor body of a first conductivity type having a first and a second main surface, at least one first semiconductor zone of a second conductivity type opposite to the first conductivity type embedded in the semiconductor body at the first main surface;
at least one second semiconductor zone of the first conductivity type provided in the at least one first semiconductor zone;
at least one gate electrode in a region above the at least one first semiconductor zone between the at least one second semiconductor zone and the semiconductor body; and
a first electrode in contact with the semiconductor body on the second main surface and a second electrode in contact with the at least one second semiconductor zone,
wherein at least one auxiliary electrode provided with an insulating layer is provided in the semiconductor body, the at least one auxiliary electrode extending in a direction between the first and the second main surfaces of the semiconductor body and being electrically connected to the at least one first semiconductor zone.
In the case of the conventional, prior art MOSFET structure such as that described in the introduction, the above mentioned object may be achieved according to the invention by virtue of the fact that at least one auxiliary electrode provided with an insulating layer is provided in the semiconductor body, which auxiliary electrode extends in the direction between the first and the second main surface of the semiconductor body and is electrically connected to the first semiconductor zone. The auxiliary electrode preferably lies directly underneath the first semiconductor zone.
In this case, it is also possible for a plurality of auxiliary electrodes of this type to be provided underneath each first semiconductor zone. These auxiliary electrodes may, if appropriate, be configured xe2x80x9cin a pencil-like mannerxe2x80x9d, as shown, for example in FIG. 1. The auxiliary electrodes may extend as far as a highly doped layer of the first conductivity type in a region near the second main surface, that is to say to a point in proximity to a drain contact zone. However, it is also possible for the auxiliary electrodes merely to reach as far as a weakly doped layer of the first conductivity type, which is provided between the semiconductor body and a heavily doped semiconductor layer of the first conductivity type in contact with the first electrode.
The auxiliary electrode itself is preferably composed of highly doped polycrystalline silicon, while silicon dioxide is preferably used for the insulating layer.
The depth of the auxiliary electrodes may, for example, be between about 5 and 40 xcexcm, while their width may be between about 1 and 5 xcexcm. The thickness of the insulating layer on the polycrystalline silicon of the auxiliary electrode may be between 0.1 and 1 xcexcm, where this thickness may increase in the direction of the second main surface or toward the center of the auxiliary electrodes between the two main surfaces.
The MOSFET according to the invention can be produced in a particularly simple manner: trenches are introduced, for example by etching, in the, for example, n-type semiconductor body. The walls and bottoms of said trenches are provided with an insulating layer, which may be produced by oxidation, with the result that, in a semiconductor body composed of silicon, a silicon dioxide layer is formed as an insulating layer. The trenches are then filled with n+- or p+-doped polycrystalline silicon.
In this case, p+-type doping is preferred for the polycrystalline silicon of the auxiliary electrode because, if a hole should be present in the insulating layer, then a blocking p-n junction is produced after p-type diffusion through the hole in the n-type semiconductor body. In the case of n+ doping for the polycrystalline silicon of the auxiliary electrode, by contrast, a short circuit to the n-type semiconductor body would be caused by such a hole.
The auxiliary electrodes themselves may be formed as pillars, grids or strips or have other configurations.
Moreover, the n-type semiconductor zones may be doped increasingly highly as the separation between the auxiliary electrodes is decreased. However, it should be taken into account in this case that, with auxiliary electrodes running parallel to one another, the lateral surface charge of the n-type semiconductor zones is not to exceed the dopant quantity corresponding to twice the breakdown charge.
The n+-type or p+-type doping in the polycrystalline silicon of the auxiliary electrodes need not be homogeneous. Rather, fluctuations in the doping concentration are readily permissible. Moreover, the depth of the auxiliary electrodes or of the trenches is not critical; these may reach as far as a highly doped drain contact zone, but need not do so.
Instead of a, for example, n-type semiconductor body, layers with different doping may also be provided for said body.